Development of EMCCD Camera Controllers

The experience of controller developers whose background is in astronomy very much puts the emphasis onto precision readout at relatively slow pixel rates. At the high pixel rates of EMCCDs, an entirely new technical approach is required in order to clock the charge efficiently and reliably at these high pixel rates without compromising other parameters such as the readout noise, dynamic range and the linearity of the CCDs. The areas that are technically rather difficult include the creation of a controller structure that allows not simply high pixel rates but can control the precise timing of the clock edges (and particularly those used by the analog to digital conversion circuitry) to a very small fraction of the pixel period. The clock drivers themselves need to be able to produce very fast clean waveforms and the signal processing system must allow the full dynamic range of the CCD even at the highest pixel rates. We use Intersil EL7156 clock driver ICs for the standard clocks, and a discrete circuit for fast pulsed high-voltage (multiplication) clock. The ADC is from Analog Devices (AD9824, 14-bit at up to 30 MHz)

The development of a controller dedicated to L3CCDs and to EMCCDs has been under way in the Institute of astronomy, University of Cambridge for some while. We were very fortunate in having Keith Weller join the team in May, 2006. He has an extensive background in electronic hardware design with considerable analogue electronics experience. Together with Frank Suess working on the camera support software excellent progress has been made.

The basic specification of the controller is given below and we are progressively improving its performance and getting closer and closer to the goal performance. We are now using an Philips LPC2148 ARM-based microcomputer with a USB interface to provide camera control from the computer. The on-board microprocessor manages a new high-speed sequencer ASIC from Kodak (KSC-1000) that allows sophisticated waveform generation at pixel rates up to 60 MHz. Using these components we now have a prototype camera taking pictures of reasonable quality at pixel rates in excess of 20 MHz. The present design needs a further refinement to improve a number of aspects of its performance but there is no doubt that we have already made very good progress in the year under report. Indeed in a number of areas we have already managed to exceed the performance specification of the controller and we can see plenty of scope for improving it further, particularly in respect of the general noise performance and immunity to interference. In particular pixel rates of up to 60 MHz now appear to be quite realistic as we have information that some devices will perform satisfactorily at these pixel rates.

EMCCD Controller System: minimum performance (desirable goal performance)

• Must operate full frame, frame transfer and interline transfer CCDs with a high-voltage multiplication gate, and with up to four phase parallel clocks in both image and store registers.
• High-voltage clocks must be able to provide 45 volt swing with 30 MHz pixel rate (for E2V L3CCDs) and 25 volt swing for 60MHz pixel rate (Texas Instruments EMCCDs)
• To operate at a pixel rate of at least 15MHz (35MHz). To provide clock drivers capable of working with at least 15 centimetres of track length between driver and CCD chip. To provide 14 bit digitisation at the maximum pixel rate with full double correlated sampling signal processing. To have the complete analog signal processing chain self calibrating and balancing to guarantee negligible fixed pattern noise.
• The structure of the controller must allow it to be expanded to cope with significant numbers of detectors (of the order of 256) being operated in parallel and simultaneously.
• The controller must be able to be operated via an industry standard ethernet/USB connection on both Windows and Linux. The data produced by the camera controller to be transmitted with high-speed LVDS drivers so that it may be attached to any industry standard frame grabber hardware that uses the AIA frame grabber interface standard.

Overall Hardware Design

The controller consists of two boards, one that generates all the clock waveforms, and one that manages the signal pre-amplification and analog to digital conversion and data transmission functions. These two boards are mounted on a third printed circuit board which is extended into the vacuum enclosure of the dewar. It is important when designing high-speed camera electronics to minimise the distance between the clock drivers and the CCD, and also to minimise the distance between the CCD and the signal processing and electronics. This latter problem can be minimised by using a buffer transistor adjacent to the CCD and this is what we have chosen to do.

Figure 1: The fibreglass spider that supports the CCD at its centre is shown here with the camera boards attached. The signal tracks enter the vacuum dewar wall indicated by the circle of holes within the fibreglass sandwich and are brought out to contacts once they are within the vacuum enclosure. Connections are also provided for monitoring and controlling the CCD temperature within the dewar. The fibreglass structure provides a rigid and reliable support for the detector while allowing it to achieve a satisfactorily low temperature.

We can make a high-quality vacuum seal by bringing all the signal tracks through the wall of the dewar on an internal PCB layer and by using a gold plated copper area to provide a reliable vacuum seal. We have used this method successfully and found that it gives a good and reliable platform for driving the CCD as well as providing a structure that is easy to work with both when it is outside the dewar and when it is within it. It also appears to have good vacuum integrity and very low out-gassing rates. Dewars using this technology seldom need vacuum pumping (typically every 1-2 years). We use dewars from Kadel Inc in the USA which are of exceptional perfprmance as well as being good value for money.

Attachment	Size
EL7156_clock_driver_020207.pdf	1.04 MB