Martin Beckett 17 Nov 96
Rockwell has recently replaced the NICMOS 256x256 MCT array with a new device called PICNIC. They are unlikely to supply any more NICMOS arrays even to fulfill current contracts. We currently have one NICMOS science grade array for COHSI along with a test device, we are waiting for the delivery of the second science grade device to make up the pair required for COHSI.
Ian Parry has talked to Kadri Vural at Rockwell and has been offered a pair of science grade arrays to replace the outstanding NICMOS device. This report discusses the technical feasibility of using PICNIC arrays in COHSI.
Some information about the PICNIC array is available on Rockwell's
web site at http://creation.risc.rockwell.com/779/mct_fpa/picnic.html
It appears that this device is a NICMOS infrared detector using a readout circuit based on the HAWAII array, this means that it has the detector characteristics of the NICMOS device, same QE, Well capacity and pixel size but has the readout scheme, clocking pattern and read noise of the HAWAII device. This means that the PICNIC device loses the NICMOS ability to reset a single pixel ( the minimum reset is now a single line ), the readout rate is reduced to about 250KHz but it gains the low read noise of the HAWAII and the ability to turn off circuitry during an exposure reducing amplifier glow.
The PICNIC device has the same pixel size and format as the NICMOS array it replaces and so there is no change to the optical system. The read noise is likely to be lower, <10 electrons are expected for the HAWAII device rather than 15-20 electrons for NICMOS. The most important parameter for COHSI is dark current, although the intrinsic dark current is unlikely to change because it is a property of the MCT material there are features built into the HAWAII mulitplexor which reduces light emission from the amplifiers and circuitry on the chip.
The PICNIC array cannot be driven with the existing hardware and software used to operate the NICMOS device, however a decision has already been made to operate the COHSI science array with the Astrocam 4100 controller using the same system as the HAWAII arrays in CIRSI. It is likely to be easier to transfer the HAWAII operating system to the PICNIC device than to the NICMOS array since the HAWAII and PICNIC arrays are very similar. Currently no detailed work has been carried out on operating the NICMOS device from the 4100 system.
We would need to obtain at least a bare PICNIC mulitplexor to allow software and hardware testing, we could avoid the need for a PICNIC engineering grade device by using experience gained in operating the HAWAII system to avoid some of the basic testing. We already have a NICMOS system for use in testing the COHSI optics.
Using a pair of PICNIC arrays on COHSI leaves us with a science
grade NICMOS device and a possibly faulty engineering grade. The
only system available to drive the NICMOS devices is not suitable
for operation on a telescope without considerable software effort,
there is currently a plan to operate the NICMOS device with the
same system as the HAWAII arrays but this looks unnecessary with
the appearance of the PICNIC device.
The PICNIC 256 X 256 readout is structured in four independent quadrants having four outputs. There are six CMOS- level clocks, two 5V power supplies (one analog and one digital). The multiplexor architecture has been optimized to minimize glow.
Each quadrant contains two digital shift registers for addressing
pixels in the array; a horizontal register and a vertical register.
Each register requires two clocks with one being a dual edge triggered
clock and one a level triggered clock. To obtain a raster scan
output, the horizontal register is usually clocked in the fast
direction with the vertical register being clocked in the slow
Pixel and Lsync are two required clocks for the
horizontal register. The Pixel input clock in a dual edge
triggered clock which will increment the selected column on both
edges (odd columns selected on positive edges and even columns
selected on negative edges). The Lsync clock is an active
low input clock which will set a "0" in the first latch
and a "1" in the remaining latches of the shift register,
thereby initializing the shift register to select the first column
in the quadrant. Since this is asynchronous to the Pixel
clock, Lsync should be pulsed low prior to initiation of
the first Pixel clock edge. The horizontal register selects which
column bus will be connected to the output Source Follower
Line and Fsync are the two required clocks for the
vertical register. The Line input clock is a dual edge
triggered clock which will increment the row selected on both
edges (odd rows selected on positive edges and even rows selected
on negative edges). The Fsync clock is an active low input
clock which will set a "0" in the first latch and a
"1" in the remaining latches of the shift register,
thereby initializing the shift register to select the first row
in the quadrant. Since this is asynchronous to the Line
clock, Fsync should be pulsed low prior to initiation of
the first Line clock edge. The vertical register selects the row
to read and/or reset depending on the Reset and Read
Correlated Double Sampling (CDS)
CDS is a clocking method by which the array is reset, sampled, allowed to integrate, and re-sampled with the difference between the 1st and 2nd samples being recorded. CDS is effective at reducing noise and eliminating detector offsets.
For long integration times, IR glow from the output Source Follower amplifiers may be evident in the image as high Dark Current areas in the corners of the array. The glow can be reduced by turning off the output Source Follower conduction during integration.
Turning off the output Source Follower amplifier can be accomplished
by ensuring that the gate of the PFET output Source Follower is
pulled high(+5V) when not in use. This occurs when the Read input
clock is pulled low, hence disconnecting all of the column buses
from the gate of the Source Follower. The gate will be pulled
up via the Biaspower bias input.
Of the 14 biases, only Vreset and Biasgate will require voltage adjustment during operation of the hybrid. Vreset is the reset voltage that gets applied to the detectors during the reset operation. This voltage is applied through an NFET reset switch which has an associated voltage drop across it due to parasitics of the reset FET; hence, this will reduce the actual voltage to the detector by about 100mV - 150mV. Vreset is usually operated in the 0.5V - 1.0V range.
Biasgate is used to adjust the speed and dynamic range
of the unit cell Source Follower. A trade off can be made between
speed and dynamic range by adjusting Biasgate from 3.3V
- 3.8V. Lower voltages increase the speed at the expense of dynamic
range, while higher voltages increase the dynamic range at the
expense of speed. A typical Biasgate voltage of 3.5V is used for
the initial characterization of the hybrid.
Source and Bus Outputs
The Source and Bus pins on the carrier are two simultaneous
outputs available on the multiplexer. Source is connected
to the source of the output Source Follower; by using a pullup
resistor of 10Kohms to +5V, the multiplexer can directly drive
off-chip loads such as cables and preamp inputs. Bus is
connected to the gate of the output Source Follower, a resistor
of 200Kohms to +5Vmay be required if the user would like to use
this output and provide their own off-chip driver.
Nicmos3 Functional Comparison
For those who are familiar with Rockwell's NICMOS3 256 x 256
SWIR focal plane array, the transition to the PICNIC
256 x 256 SWIR focal plane array should be relatively easy;
however, there have been some slight changes to the basic architecture
which should be noted:
In an attempt to reduce the effects of noise caused by resetting
pixels in the array (reset anomaly), the PICNIC multiplexer
has a line by line reset instead of a pixel by pixel reset. This
means that at any time while accessing a row, the entire row will
be reset when Reset clock is pulsed high. In order to reset
an entire frame of a NICMOS3, it is necessary to address
every pixel in a quadrant. In order to reset an entire frame of
a PICNIC multiplexer, it is necessary only to clock through
the vertical register.
Both NIMOS3 and PICNIC require six input clocks to properly operate the array. Both require two clocks per shift register; however, for PICNIC, Lsync should be pulsed low before the first pixel clock edge for the horizontal register and not during, as is the case with the NICMOS3. This is also true for Fsync and Line inputs for the vertical register. The Line clock for PICNIC is dual edge triggered, not negative edge triggered as in the NICMOS3.
The two remaining clocks inputs are Reset and Read.
While accessing any row in the array, pulling the Reset input
high will simultaneously reset all pixels in that row; this is
in contrast to NICMOS3 which requires the accessing of every pixel
which is to be reset. By pulling the Read input high, the
currently selected unit cell Source Follower is allowed to pass
to the column bus. This also means that anytime the Read
clock is low, none of the unit cell signals can be transferred
to the output Source Follower via the column busses; regardless
of the state of the horizontal or vertical registers. This
feature is very useful in turning "off" the output Source
Follower when not in use to decrease the effects of the output
Source Follower glow. NICMOS3 requires an extra horizontal
register Pixel clock at the end of the row in order to
ensure that the output Source Follower was "off".